State of the art electronic design automation (EDA) systems for designing complex integrated circuits (ICs) involves the use of several software tools for the creation and verification of designs of such circuits. Presently, EDA systems implement a design process commonly known as the top-down design methodology. This methodology is an iterative process that includes the processing steps of logic synthesis, floor planning, place and route, parasitic extraction, and timing optimization.
The start point of a typical top-down design flow is a register transfer level (RTL) description of a circuit. The RTL description provides a functional view of an IC design expressed in a hardware description language (HDL). This design is coupled with various design goals, such as the overall operating frequency of the IC, circuit area, power consumption, and the like. The RTL description (or model) is manually partitioned by a designer into various functional blocks that together represent the functional and architectural characteristics of the design. The functional blocks are then converted by logic synthesis tools into detailed gate level netlists. A synthesis tool further determines the timing constraints based on statistical and placement-based wire-load estimation models and pre-characterized cell libraries for the process technology to be used when physically implementing the IC. The gate-level netlist and timing constraints are then used to create a floor-plan of the circuit. Thereafter, blocks are placed and routed by place-and-route tools to create the physical layout.
Presently, the complexity of IC designs overwhelms the capability of logic synthesis tools. For example, the synthesis execution time of a typical IC containing only tens of thousands of logic gates is typically on the order of days.
Most RTL synthesis tools provide two levels of connectivity representation: 1) a bus level and 2) a bit level. The bit level representation is equivalent to wire connections and the objects of this representation are bit nets and bit pins. The bit pins may be either cell pins or inst-pins. In integrated circuit design, pins refer to a way of representing interconnects such as actual pins and/or wires. The cell pins are used to link between cells and inst-pins are for connecting nets. The bus level representation is equivalent to the source RTL. The objects of this representation, in addition to the bit nets and bit pins, are multi-bit nets (or busses) and multi-bit pins. The bit level representation can be generated from a given bus level representation. The bus representation is used solely for generating HDL code and for schematic display purposes. The bit level representation is used in tasks executed to optimization and analysis tools, such partitioning, restructuring, sizing, global placement, routing, and so on.
FIG. 1 schematically shows the difference between the bit and bus level representations, both being compliant with the following RTL description.                module inv (out, in)                    output[7:0] out;            input[7:0] in;            out=˜in;                        end module        
FIG. 1A depicts a bus level representation of the above ‘inv’ module that includes two multi-bit nets 110 and 120, respectively associated with the ‘in’ and ‘out’ busses. The equivalent bit level representation depicted in FIG. 1B includes 16 bit nets, where nets 130-0 through 130-7 represent wires of the ‘in’ bus and nets 130-8 through 130-15 are wires of the ‘out’ bus. In fact, a bit level netlist for the above module includes 16 nets, 16 inst-pins and 16 cell pins.
As can be noted, the bit level representation increases the network complexity, i.e., the number of wires in the netlist. In general, the bus representation is the most compact representation, but it does not explicitly capture the connectivity. Therefore, traversing of a bus level netlist by optimization and analysis tools is inefficient and error prone. On the other hand, a bit level netlist explicitly captures the connectivity, thus making traversals efficient. However, this representation is complex and incomprehensible to an IC designer.
Therefore, in view of the limitations of the prior art, it would be advantageous to provide a connectivity abstraction method that maintains the compactness of a bus level representation while ensuring the explicit connectivity capture of a bit level representation.